(1) Field of the Invention
The invention relates to the manufacture of highly dense integrated circuits and more particularly to the formation of metal oxide silicon field effect devices and double polycrystalline silicon capacitors within the integrated circuit.
(2) Description of the Prior Art
In recent years there continues to be dramatic density increases in the integrated circuit technology. The minimum feature size of lithography has been reduced to one minimum feature size of lithography has been reduced to one micrometer and below. As would be expected,, manufacturing problems involving device yield, reliability and cost have increased with this reduction in feature size.
One of the problems encountered is the polycrystalline silicon "stringer". These "stringer" are unwanted leftovers from etching, usually a directional reactive ion etch of a layer of polycrystalline silicon over irregular surfaces. To remove these "stringer" it is necessary to overetch the polycrystalline silicon layer which results in an undesired thinner layer, linewidth reduction and/or damage to the underlayer.
This "stringer" problem has been encountered in the DRAM technology and a solution patented by T. A. Lowrey et al U.S. Pat. No. 4,957,878. The problem was encountered where the capacitor to substrate layer was the polysilicon layer I and the gate electrode of the transistor was polysilicon II. The novel solution was to reverse the layer applications, that is the polysilicon layer 1 was made the transistor gate electrode and the polysilicon layer II was made the capacitor to substrate layer. This approach in DRAM technology establishes the critical dimensions at preliminary mask layers and subsequent layers do not require the high degree of criticality of dimension.
The "stringer" problem that applicant is concerned with involves the formation of an analog integrated circuit composed of a double polycrystalline capacitor and a field effect transistor combination, not the DRAM integrated circuit technology of the above described Lowery et al Patent.
The FIGS. 1 through 4 shows the process that is used to manufacture the double polycrystalline silicon capacitor and field effect transistor integrated circuit which has the "stringer" problem. FIG. 1 shows a monocrystalline silicon semiconductor substrate 10 having a pattern 12 or FOX (field oxide) of recessed oxide isolation on the surface of the silicon substrate which pattern separates surface regions of silicon from other such regions. A polycrystalline silicon layer 14 is blanket deposited and doped over the surfaces and then patterned by lithography and etching techniques to leave the polysilicon I layer 14 as the bottom plate for the capacitor on the recessed oxide isolation 12. An interpoly layer 16 composed of, for example silicon oxide layer 18 and silicon nitride layer 20 are formed over the structure and the silicon nitride layer is patterned by lithography and etching to give the FIG. 1 structure.
FIG. 2 shows the structure after the deposition of polysilicon layer II 22. Lithography and etching of the FIG. 2 layer 22 is accomplished by formation of resist masking layer 24 as seen in FIG. 3. The etching leaves the top plate of the capacitor 25 and the gate electrode 23 of the field effect transistor device. However, the unwanted "stringers" 30 are left on the irregular surfaces, such as seen around the edge of polysilicon I 14. This is very difficult to fully remove even with the overetching of the polysilicon II layer. The process continues to produce the FIG. 4 structure by the lightly doped ion implantation to form N-regions 32, sidewall oxide regions 34, heavily doped ion implantation to form N+ regions 36, passivation layer 38 and metallurgy contacts 40 to the various elements of the integrated circuits. However, some of the "stringers" 30 still remain in the structure even with overetching.
The present of "stringers" in this analog integrated circuit of FIG. 4 is a problem because the use of overetching to remove these "stringers" is incompatible with submicrometer processing. The reason is that submicron devices have thinner gate oxide under the polysilicon II electrode. Overetching can cause damage to the substrate as thinner gate oxide is more difficult to withstand overetching. In addition, overetching produces linewidth loss whose magnitude varies with pattern density (known as microloading effect), contributing to the linewidth variation of polysilicon critical dimension, a more serious problem for submicron processing.